元器件交易网www.cecb2b.com SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS300I – JANUARY 1993 – REVISED JUNE 1998DEPIC™ (Enhanced-Performance ImplantedDDDDDDDCMOS) Submicron ProcessTypical VOLP (Output Ground Bounce)< 0.8 V at VCC = 3.3 V, TA = 25°CTypical VOHV (Output VOH Undershoot)> 2 V at VCC = 3.3 V, TA = 25°CSupport Mixed-Mode Signal Operation onAll Ports (5-V Input/Output Voltage With3.3-V VCC)Power Off Disables Outputs, PermittingLive InsertionESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 250 mA PerJESD 17Package Options Include PlasticSmall-Outline (DW), Shrink Small-Outline(DB), Thin Shrink Small-Outline (PW), andCeramic Flat (W) Packages, Ceramic ChipCarriers (FK), and DIPs (J)SN54LVC573A...J OR W PACKAGESN74LVC573A...DB, DW, OR PW PACKAGE(TOP VIEW)OE1D2D3D4D5D6D7D8DGND1234567891020191817161514131211VCC1Q2Q3Q4Q5Q6Q7Q8QLE SN54LVC573A...FK PACKAGE(TOP VIEW)2D1DOEVCCdescriptionThe SN54LVC573A octal transparent D-type latchis designed for 2.7-V to 3.6-V VCC operation andthe SN74LVC573A octal transparent D-type latchis designed for 1.65-V to 3.6-V VCC operation.3D4D5D6D7D45678321201918171615149101112131Q2Q3Q4Q5Q6QThese devices feature 3-state outputs designed specifically for driving highly capacitive or relativelylow-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,bidirectional bus drivers, and working registers.While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, theQ outputs are latched at the logic levels at the D inputs.A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (highor low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drivethe bus lines significantly. The high-impedancestate and increased drive provide the capability to drive buslines without interface or pullup components.OE does not affect the internal operations of the latches. Old data can be retained or new data can be enteredwhile the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translatorsin a mixed 3.3-V/5-V system environment.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.EPIC is a trademark of Texas Instruments Incorporated.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright © 1998, Texas Instruments IncorporatedOn products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•8DGNDLE8Q7Q1元器件交易网www.cecb2b.comSCAS300I – JANUARY 1993 – REVISED JUNE 1998SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSdescription (continued) The SN54LVC573A is characterized for operation over the full military temperature range of –55°C to 125°C.The SN74LVC573A is characterized for operation from –40°C to 85°C.FUNCTION TABLE(each latch)INPUTSOELLLHLEHHLXDHLXXOUTPUTQHLQ0Zlogic symbol†OELE1D2D3D4D5D6D7D8D11123456789ENC11D19181716151413121Q2Q3Q4Q5Q6Q7Q8Q†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.logic diagram (positive logic)OE1LE11C1191D21D1QTo Seven Other Channels2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS300I – JANUARY 1993 – REVISED JUNE 1998absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 VVoltage range applied to any output in the high-impedance or power-off state, VO(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 VVoltage range applied to any output in the high or low state, VO(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 VInput clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mAOutput clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mAContinuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mAPackage thermal impedance, θJA (see Note 3):DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/WDW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/WPW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/WStorage temperature range, Tstg –65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The value of VCC is provided in the recommended operating conditions table.3.The package thermal impedance is calculated in accordance with JESD 51.recommended operating conditions (see Note 4)SN54LVC573AMINVCCSupplyvoltageSupply voltageOperatingData retention onlyVCC = 1.65 V to 1.95 VVCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 VVCC = 1.65 V to 1.95 VVILVIVOLow-level input voltageInput voltageOutputvoltageOutput voltageHigh or low state3 stateVCC = 1.65 VVCC = 2.3 VVCC = 2.7 VVCC = 3 VVCC = 1.65 VVCC = 2.3 VVCC = 2.7 VVCC = 3 V0122460–12–24VCC = 2.3 V to 2.7 VVCC = 2.7 V to 3.6 V000221.5MAX3.6SN74LVC573AMIN1.651.50.65 ×VCC1.720.35 ×VCC0.70.85.5VCC5.50000.85.5VCC5.5–4–8–12–244812246ns/VmAmAVVVVMAX3.6UNITVVIHHigh-level input voltageIOHHighleveloutputcurrentHigh-level output currentIOLLowleveloutputcurrentLow-level output current∆t/∆vInput transition rise or fall rateTAOperating free-air temperature–55125–4085°CNOTE 4:All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCAS300I – JANUARY 1993 – REVISED JUNE 1998SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTESTCONDITIONSTEST CONDITIONSIOH = –100 =100µAIOH = –4 mAIOH = –8 mAIOH = –12 mA=12mAIOH = –24 mA=100µAIOL = 100 VOLIOL = 4 mAIOL = 8 mAIOL = 12 mAIOL = 24 mAIIIoffIOZICC∆ICCCiCoVI = 0 to 5.5 VVI or VO = 5.5 VVO = 0 to 5.5 VVI = VCC or GND3.6 V ≤ VI ≤ 5.5 V‡VCC1.65 V to 3.6 V2.7 V to 3.6 V1.65 V2.3 V2.7 V3 V3 V1.65 V to 3.6 V2.7 V to 3.6 V1.65 V2.3 V2.7 V3 V3.6 V03.6 VIO = 0=036V3.6 V2.7 V to 3.6 V3.3 V3.3 V45.5±15101050045.50.40.55±50.20.450.70.40.55±5±10±101010500µAµAµAµAµApFpFV2.22.42.2VCC–0.21.21.72.22.42.20.2VSN54LVC573AMINTYP†MAXSN74LVC573AMINTYP†MAXVCC–0.2UNITVOHOne input at VCC – 0.6 V,Other inputs at VCC or GNDVI = VCC or GNDVO = VCC or GND†All typical values are at VCC = 3.3 V, TA = 25°C.‡This applies in the disabled state only.timing requirements over recommended operating free-air temperature range (unless otherwisenoted) (see Figure 3)SN54LVC573AVCC = 2.7 VMINtwtsuthPulse duration, LE highSetup time, data before LE↓Hold time, data after LE↓3.322.5MAXVCC = 3.3 V± 0.3 VMIN3.322.5MAXnsnsnsUNIT4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS300I – JANUARY 1993 – REVISED JUNE 1998timing requirements over recommended operating free-air temperature range (unless otherwisenoted) (see Figures 1 through 3)SN74LVC573AVCC = 1.8 V± 0.15 VMINtwtsuPulse duration, LE highSetup time, data before LE↓†††MAXVCC = 2.5 V± 0.2 VMIN†††MAXVCC = 2.7 VMIN3.321.5MAXVCC = 3.3 V± 0.3 VMIN3.321.5MAXnsnsnsUNITthHold time, data after LE↓†This information was not available at the time of publication.switching characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figure 3)SN54LVC573APARAMETERFROM(INPUT)DLEOEOETO(OUTPUT)VCC = 2.7 VMINtpddtentdisQQQMAX7.78.48.57VCC = 3.3 V± 0.3 VMIN1110.5MAX6.97.77.56.7nsnsnsUNITswitching characteristics over recommended operating free-air temperature range (unlessotherwise noted) (see Figures 1 through 3)SN74LVC573APARAMETERFROM(INPUT)DLEOEOETO(OUTPUT)VCC = 1.8 V± 0.15 VMINtpddtentdistsk(o)‡†This information was not available at the time of publication.‡Skew between any two outputs of the same package switching in the same directionQQQ††††MAX††††VCC = 2.5 V± 0.2 VMIN††††MAX††††VCC = 2.7 VMINMAX7.78.48.57VCC = 3.3 V± 0.3 VMIN1.521.51.6MAX6.97.77.56.51nsnsnsnsUNIToperating characteristics, TA = 25°CPARAMETERPower dissipation capacitanceper latchOutputs enabledOutputs disabledTESTCONDITIONSf=10MHzf = 10 MHzVCC = 1.8 V± 0.15 VTYP††VCC = 2.5 V± 0.2 VTYP††VCC = 3.3 V± 0.3 VTYP374pFUNITCpd†This information was not available at the time of publication.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comSCAS300I – JANUARY 1993 – REVISED JUNE 1998SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSPARAMETER MEASUREMENT INFORMATIONVCC = 1.8 V ± 0.15 V1k ΩS12 × VCCOpenGND1k ΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCOpen From OutputUnder TestCL = 30 pF(see Note A)LOAD CIRCUITVCC0 VtsuDataInputVCC/2thVCCVCC/20 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVCCInputVCC/2tPLHOutputVCC/2VOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVCC/20 VtPHLVOHVCC/2VOLOutputWaveform 2S1 at Open(see Note B)OutputControl(low-levelenabling)tPZLOutputWaveform 1S1 at 2 × VCC(see Note B)tPZHtwInputVCC/2VOLTAGE WAVEFORMSPULSE DURATIONVCCVCC/2VCC/20 VtPLZVCCVCC/2VOL + 0.15 VVOLtPHZVCC/2VOHVOH – 0.15 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESVCC/2VCC0 VTimingInputVCC/2NOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 1. Load Circuit and Voltage Waveforms6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS300I – JANUARY 1993 – REVISED JUNE 1998PARAMETER MEASUREMENT INFORMATIONVCC = 2.5 V ± 0.2 V500 ΩS12 × VCCOpenGND500 ΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCGNDFrom OutputUnder TestCL = 30 pF(see Note A)LOAD CIRCUITVCC0 VtsuDataInputVCC/2thVCCVCC/20 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVCCInputVCC/2tPLHOutputVCC/2VOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVCC/20 VtPHLVOHVCC/2VOLOutputWaveform 2S1 at GND(see Note B)OutputControl(low-levelenabling)tPZLOutputWaveform 1S1 at 2 × VCC(see Note B)tPZHtwInputVCC/2VOLTAGE WAVEFORMSPULSE DURATIONVCCVCC/2VCC/20 VtPLZVCCVCC/2VOL + 0.15 VVOLtPHZVCC/2VOHVOH – 0.15 V0 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESVCC/2VCC0 VTimingInputVCC/2NOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2 ns, tf≤2 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 2. Load Circuit and Voltage WaveformsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.comSCAS300I – JANUARY 1993 – REVISED JUNE 1998SN54LVC573A, SN74LVC573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSPARAMETER MEASUREMENT INFORMATIONVCC = 2.7 V AND 3.3 V ± 0.3 V6 VFrom OutputUnder TestCL = 50 pF(see Note A)500 ΩS1OpenGND500 ΩTESTtpdtPLZ/tPZLtPHZ/tPZHS1Open6 VGND LOAD CIRCUITtw2.7 VTimingInputtsuDataInput1.5 V2.7 V1.5 V0 Vth2.7 V1.5 V0 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESInput1.5 V1.5 V0 VVOLTAGE WAVEFORMSPULSE DURATIONOutputControl(low-levelenabling)tPZLOutputWaveform 1S1 at 6 V(see Note B)OutputWaveform 2S1 at GND(see Note B)tPZH2.7 V1.5 V1.5 V0 VtPLZ3 V1.5 VtPHZVOH – 0.3 VVOL + 0.3 VVOL2.7 VInputtPLH1.5 V1.5 V0 VtPHLVOHOutput1.5 VVOLTAGE WAVEFORMSPROPAGATION DELAY TIMES1.5 VVOLVOH0 V1.5 VVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr≤2.5 ns, tf≤2.5 ns.D.The outputs are measured one at a time with one transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPLH and tPHL are the same as tpd.Figure 3. Load Circuit and Voltage Waveforms8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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