19-0147; Rev. 1; 4/94Microprocessor and Non-VolatileMemory Supervisory Circuits_______________General DescriptionThe MAX792/MAX820 microprocessor (µP) supervisorycircuits provide the most functions for power-supplyand watchdog monitoring in systems without batterybackup. Built-in features include the following:
1)µP reset: Assertion of RESET and RESEToutputs dur-ing power-up, power-down, and brownout conditions.RESETis guaranteed valid for VCCdown to 1V.2)Manual-reset input.
3)Two-stage power-fail warning: A separate low-line
comparator compares VCCto a preset threshold120mV above the reset threshold; the low-line andreset thresholds can be programmed externally.4)Watchdog fault output: Assertion of WDOif the watch-dog input is not toggled within a preset timeout period.____________________________FeaturesoManual-Reset Input
o200ms Power OK/Reset Time Delay
oIndependent Watchdog Timer—Preset or AdjustableoOn-Board Gating of Chip-Enable SignalsoMemory Write-Cycle Completion
o10ns (max) Chip-Enable Gate Propagation DelayoVoltage Monitor for Overvoltage Warningo±2% Reset and Low-Line Threshold Accuracy(MAX820, external programming mode)
MAX792/MAX820______________Ordering InformationPART**TEMP. RANGEPIN-PACKAGE5)Pulsed watchdog output: Advance warning of
MAX792_CPE0°C to +70°C16 Plastic DIPimpending WDOassertion from watchdog timeoutthat causes hardware shutdown.
MAX792_CSE0°C to +70°C16 Narrow SO6)Write protection of CMOS RAM, EEPROM, or other
MAX792_C/D
0°C to +70°C
Dice*
memory devices.
Ordering Information continued on last page.* Dice are tested at TThe MAX792 and MAX820 are identical, except theA= +25°C, DC parameters only.MAX820 guarantees higher low-line and reset threshold**These parts offer a choice of five different reset threshold volt-ages. Select the letter corresponding to the desired nominalaccuracy (±2%).
reset threshold voltage and insert it into the blank to complete the________________________Applicationspart number.ComputersSUFFIX
RESET THRESHOLD (V)Controllers
ML
4.62Intelligent Instruments
T4.37S3.06Critical µP Power Monitoring
R
2.912.61
___________________________________________________Typical Operating CircuitVCC30.1µFVCCVCC4CE OUT13RESET IN/INTµPMAX792RAM5LLIN/CE IN14ADDRESSREFOUTDECODERA0-A15OVO6LOW LINE10NMI7OVIRESET1RESET8SWTMR9GNDGND12________________________________________________________________Maxim Integrated Products1
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Microprocessor and Non-Volatile MemorySupervisory CircuitsMAX792/MAX820ABSOLUTE MAXIMUM RATINGS
Input Voltage (with respect to GND)
VCC.......................................................................-0.3V to +6VAll Other Inputs.......................................-0.3V to (VCC+ 0.3V)Input Current
GND................................................................................25mAAll Other Outputs............................................................25mAContinuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C)..........842mWNarrow SO (derate 9.52mW/°C above +70°C)............762mWCERDIP (derate 10.00mW/°C above +70°C)...............800mW
Operating Temperature Ranges:
MAX792_C__/MAX820_C__...............................O°C to +70°CMAX792_E__/MAX820_E__.............................-40°C to +85°CMAX792_MJE__/MAX820_MJE__..................-55°C to +125°CStorage Temperature Range.............................-65°C to +160°CLead Temperature (soldering, 10sec).............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.ELECTRICAL CHARACTERISTICS
(VCC= 2.55V to 5.5V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETEROperating Voltage RangeSupply CurrentRESET COMPARATORMAX792L, MAX820LMAX792M, MAX820MMAX792R, MAX820RReset Threshold Voltage—Internal Threshold Mode (VTH)MAX792S, MAX820SMAX792T, MAX820TMAX820L, TA= +25°C, VCCfallingMAX820M, TA= +25°C, VCCfallingMAX820R, TA= +25°C, VCCfallingMAX820S, TA= +25°C, VCCfallingMAX820T, TA= +25°C, VCCfallingMAX792, VCC= 5V or VCC= 3VMAX820, VCC= 5V or VCC= 3VInternal threshold mode4.504.252.552.853.004.554.302.552.853.001.251.2744.624.372.612.913.064.754.502.703.003.154.704.452.662.963.111.351.32660±0.01±250.016 x VTH702002800.010.30.10.4VCONDITIONSMIN2.5570150TYPMAXUNITSVµAReset Threshold VoltageExternal Threshold Mode (VTH)RESET IN/INTMode Threshold(Note 1)RESET IN/INTLeakage CurrentReset Threshold HysteresisReset Comparator DelayReset Active Timeout Period1.301.30VmVnAVµsmsRESETOutput VoltageRESET Output VoltageVCCfallingVCCrisingISINK= 50µA, VCC= 1V, VCCfallingISINK= 1.6mAISOURCE= 1mAISOURCE= 100µAISINK= 1.6mAISOURCE= 1mAISOURCE= 100µA140VCC- 1VCC- 0.50.1VCC- 1VCC- 0.50.4VV2_______________________________________________________________________________________
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Microprocessor and Non-Volatile MemorySupervisory CircuitsELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.55V to 5.5V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERLOW-LINE COMPARATORLow-Line Threshold Voltage(Internal Threshold Mode)—VTHLow-Line Threshold Voltage(External Programming Mode) Low-Line Hysteresis (Internal Threshold Mode)LLIN/REFOUT Leakage CurrentExternal Programming ModeLow-Line Comparator DelayVCCfallingMAX792/MAX820CONDITIONSMAX792/MAX820L/MMAX792/MAX820R/S/TMAX792, VCC= 5V OR VCC= 3VMAX820, VCC= 5V OR VCC= 3VMIN50401.251.274TYP1201001.301.3020±0.01450MAX2002001.351.326UNITSmVVmV±25nAµsLOWLINEVoltageISINK= 3.2mA0.4ISOURCE= 1µAVCC- 1VLOWLINEShort-Circuit CurrentOutput source current, VCC= 5.5V1050µAWATCHDOG FUNCTIONSWT connected to VCC, VCC = 5V1.001.602.25SWT connected to VCC, VCC = 3V1.001.602.25secWatchdog Timeout Period4.7nF capacitor connected from SWT to GND,VCC = 3V704.7nF capacitor connected from SWT to GNDms,VCC = 5V100Watchdog Input Pulse WidthVIL= 0V, VIH= VCCVCC= 3V100VCC= 5V300nsISINK= 50µA, VCC= 1V, VCCfalling0.010.30WDOOutput VoltageISINK= 1.6mA0.10.4ISOURCE= 1mAVCC- 1VISOURCE= 100µAVCC- 0.5WDPOto WDODelay70nsWDPODuration0.51.76.0msISINK= 50µA, VCC= 1V, VCCfalling0.010.3WDPOOutput VoltageISINK= 1.6mA0.10.4ISOURCE= 1mAVCC- 1VISOURCE= 100µAVCC- 0.5VCC= 4.25VVIH0.75 x VCCWDI Threshold VoltageVIL0.8VCC= 2.55VVIH0.9 x VCCVVIL0.2WDI Input Current±1µA_______________________________________________________________________________________3
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Microprocessor and Non-Volatile MemorySupervisory CircuitsMAX792/MAX820ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.55V to 5.5V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETEROVERVOLTAGE COMPARATOROVI Input ThresholdOVI Leakage CurrentOVO Output VoltageOVOShort-Circuit CurrentOVI to OVODelayCHIP-ENABLE GATINGVCC = 4.25VCEINThreshold VoltageVCC= 2.55VCEIN Leakage CurrentCEIN to CEOUT ResistanceCEOUT Short-Circuit CurrentChip-Enable Propagation Delay(Note 2)Chip-Enable Output VoltageHigh (Reset Active)Reset Active to CEOUT HighMANUAL RESETMRMinimum Pulse WidthMRtoRESETPropagationDelayMRThreshold RangeMRPull-Up CurrentMR= 0VVCC= 4.25Vto VCC= 5.5VVCC= 2.5V1.151Disabled modeEnabled modeDisabled mode, CEOUT= 0V50Ωsource impedance driver,CLOAD= 50pFIOUT= -100µAIOUT= 10µAVCC fallingVCC= 5VVCC= 3VVCC= 5VVCC= 3VVCC= 5VVCC= 3VVCC- 1VCC- 0.51525121.3231.580VIHVILVIHVIL0.75 x VCC0.80.75 x VCC±0.005751500.50.050.2680.2±11503002.50.41013VISINK= 3.2mAISOURCE= 1µAOutput source current, VCC= 5.5VVOD= 100mV, OVI risingVOD= 100mV, OVI fallingVCC- 110135550VCC= 5V or VCC= 3V1.251.30±0.011.35±250.4VnAVµAµsCONDITIONSMINTYPMAXUNITSµAΩmAnsVµsµsµsVµANote 1:Pulling RESET IN/INTbelow 60mV selects internal threshold mode and connects the internal voltage divider to the reset
and low-line comparators. External programming mode allows an external resistor divider to set the low-line and resetthresholds (see Figure 4).
Note 2:The Chip-Enable Propagation delay is measured from the 50% point at CEIN to the 50% point at CEOUT.
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Microprocessor and Non-Volatile Memory Supervisory Circuits__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX792-1MAX792/MAX820OVERVOLTAGE COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
MAX792-290SUPPLY CURRENT (µA)8070605040302010VCC = 5VPROPAGATION DELAY (µs)60
PROPAGATION DELAY (µs)SWT = VCCALL OUTPUTSUNLOADED70
VCC = 4VVCC = 3V5060
40
VCC = 2VVIH TO VOLVIN = 20mVOVERDRIVE = 15mV50
VCC FALLING15mV OVERDRIVEMAX792-3100
RESET COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
80
70
030
40
EXTERNAL PROGRAMMING MODE-60
-30
0
30
60
90
120
150
-60
-30
0
30
60
90
120
150
-60
-30
0
30
60
90
120150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LOW-LINE COMPARATOR
POWER-UP RESET DELAYNOMINAL WATCHDOG TIMEOUT
PROPAGATION DELAY vs. TEMPERATURE
vs. TEMPERATURE
PERIOD vs. VCC
)600300ca34e3.0
5---222999s777(XXX AAAMMDMOI)Rs500
250EµP(VCC = 5V 2.5
YTAUL200)OEsED400
mM IN( TOY G2.0
IA150TLOA300
EGDVDAHCPCC = 3V100TOARPW1.5
200V CC FALLINGL15mV OVERDRIVEA50NIEXTERNAL PROGRAMMING MODEM100
O0
N1.0
-60
-30
0
30
60
90
120
150
-60-300306090120150
2
3
4
5
TEMPERATURE (°C)TEMPERATURE (°C)
VCC (V)
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX820____________________________Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
INTERNAL-MODE RESET THRESHOLDvs. TEMPERATURE (NORMALIZED)
MAX792-6REF OUT VOLTAGEvs. TEMPERATURE
MAX792-7CHIP-ENABLE ON-RESISTANCE
vs. TEMPERATURE
180160ON-RESISTANCE (Ω)140120100806040
VCC = 5VVCE IN = 2.5VVCC = 3VVCE IN = 1.5VMAX792-81.1251.1001.075RESET THRESHOLD1.331.321.31REF OUT (V)1.301.291.281.27
200
1.0501.0251.0000.9750.9500.9250.900
-60
THE RESET THRESHOLD IS SHOWNNORMALIZED TO 1, REPRESENTINGALL AVAILABLE MAX792/MAX820-30
0
30
60
90
120150
1.261.25
-60
-30
0
30
RESET IN / INT = 0V60
90
120
150
200-60
-30
0
30
60
90
120150
TEMPERATURE (°C)
TEMPERATURE (°C)TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIODvs. SWT LOAD CAPACITANCE
MAX792-10CHIP-ENABLE PROPAGATION DELAYvs. CE OUT LOAD CAPACITANCEVCC = +5VVCE IN = 0V TO 5VDRIVER SOURCEIMPEDANCE = 50ΩMAX792-11100kWATCHDOG TIMEOUT PERIOD (ms)20
10k
PROPAGATION DELAY (ns)1µ
15
1k
VCC = 5VVCC = 3V10
1005
10
1n
10n
CSWT (F)
100n
0
0
255075100125150175200225250
CLOAD (pF)
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Microprocessor and Non-VolatileMemory Supervisory Circuits______________________________________________________________Pin DescriptionPIN
NAMERESET
FUNCTION
Active-Low Reset Output goes low whenever VCCfalls below the reset threshold in internal thresh-old programming mode, or RESET IN falls below 1.30V in external threshold programming mode.RESETremains low for 200ms typ after the threshold is exceeded on power-up.Reset is the inverse of RESET.Input Supply Voltage
Reset-Input/Internal-Mode Select. Connect this input to GND to select internal threshold mode.Select external programming mode by pulling this input 600mV or higher through an external volt-age divider.
Low-Line Input/Reference Output connects directly to the low-line comparator in external program-MAX792/MAX8201
234
RESETVCCRESET IN/INT
5LLIN/REF OUT
ming mode (RESET IN/INT≥600mV). Connects directly to the internal 1.30V reference in internalthreshold mode (RESET IN/INT≤ 60mV).
6OVO
Overvoltage Comparator Output goes low when OVI is greater than 1.30V. This is an uncommittedcomparator and has no effect on any other internal circuitry.
7OVI
Inverting Input to the Overvoltage Comparator. When OVI is greater than 1.30V, OVOgoes low.Connect OVI to GND or VCCwhen not used.
Set Watchdog-Timeout Input. Connect this input to VCCto select the default 1.6sec watchdog8SWT
timeout period. Connect a capacitor between this input and GND to select another watchdog-timeout period. Watchdog timeout period = k x (capacitor value in nF)mV, where k = 27 for VCC= 5V and k = 16.2 for VCC= 3V. If the watchdog function is unused, connect SWT to VCC.9MR
Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to alogic gate output. Internally pulled up to VCC.
10LOW LINE
Low-Line Output. LOW LINEgoes low 120mV above the reset threshold in internal thresholdmode, or when LLIN/REFOUT goes below 1.30V in external programming mode.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period,11WDI
WDPOpulses low and WDOgoes low. WDOremains low until the next transition at WDI. Connectto GND or VCCif unused.12GND
Ground
Chip-Enable Output. CEOUT goes low only when CEIN is low and reset is not asserted. If CEIN13CEOUT
is low when reset is asserted, CEOUT will stay low for 15µs or until CEIN goes high, whicheveroccurs first.
14CEIN
Chip-Enable Input—the input to the chip-enable transmission gate. Connect to GND or VCCif notused.
15WDO
Watchdog Output. WDOgoes low if WDI remains either high or low longer than the watchdogtimeout period. WDOreturns high on the next transition at WDI.
16WDPO
Watchdog-Pulse Output. Upon the absence of a transition at WDI, WDPOwill pulse low for a mini-mumof 500µs. WDPOprecedes WDOby typically 70ns.
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX820_______________Detailed DescriptionManual-Reset InputMany µP-based products require manual-reset capabil-ity, allowing the operator to initiate a reset. The manu-al/external-reset input (MR)can connect directly to aswitch without an external pull-up resistor or debounc-ing network. MRinternally connects to a 1.30V com-parator, and has a high-impedance pull-up to VCC, asshown in Figure 1. The propagation delay from assert-ing MRto reset asserted is typically 12µs. Pulsing MRlow for a minimum of 25µs asserts the reset function(see Reset Functionsection). The reset output remainsactive as long as MRis held low, and the reset timeoutperiod begins after MRreturns high (Figure 2). To pro-vide extra noise immunity in high-noise environments,pull MRup to VCCwith a 100kΩresistor.
Use MRas either a digital logic input or as a second low-line comparator. Normal TTL/CMOS levels can bewire-OR connected via pull-down diodes (Figure 3),and open-drain/collector outputs can be wire-OReddirectly.
Monitoring the Regulated SupplyThe MAX792/MAX820 offer two modes for monitoringthe regulated supply and providing reset and non-maskable interrupt (NMI) signals to the µP: internalthreshold mode uses the factory preset low-line andreset thresholds, and external programming modeallows the low-line and reset thresholds to be pro-grammed externally using a resistor voltage divider(Figure 4).
Internal Threshold ModeConnecting the reset-input/internal-mode select pin(RESET IN/INT) to ground selects internal thresholdmode (Figure 4a). In this mode, the low-line and resetthresholds are factory preset by an internal voltagedivider (Figure 1) to the threshold voltages specified inthe Electrical Characteristics(Reset Threshold Voltageand Low-Line Threshold Voltage). Connect the low-lineoutput (LOWLINE) to the µP NMI pin, and connect theactive-high reset output (RESET) or active-low resetoutput (RESET) to the µP reset input pin.
Additionally, the low-line input/reference-output pin(LLIN/REFOUT) connects to the internal 1.30V refer-ence in internal threshold mode. Buffer LLIN/REFOUTwith a high-impedance buffer to use it with externalcircuitry. In this mode, when VCCis falling, LOWLINEisguaranteed to be asserted prior to reset assertion.
External Programming ModeConnecting RESET IN/INTto a voltage above 600mVselects external programming mode. In this mode, thelow-line and reset comparators disconnect from the inter-nal voltage divider and connect to LLIN/REFOUT andRESET IN/INT, respectively (Figure 1). This mode allowsflexibility in determining where in the operating voltagerange the NMI and reset are generated. Set the low-lineand reset thresholds with an external resistor divider, as inFigure 4b or Figure 4c. RESET typically remains valid forVCCdown to 2.5V; RESETis guaranteed to be valid withVCCdown to 1V.
Calculate the values for the resistor voltage divider inFigure 4b using the following equations:
1) R3 = (1.30 x VCCMAX)/(VLOW LINEx IMAX)2) R2 = [(1.30 x VCCMAX)/(VRESETx IMAX)] - R33) R1 = (VCCMAX/IMAX) - (R2 + R3).
First choose the desired maximum current through thevoltage divider (IMAX) when VCCis at its highest (VCCMAX). There are two things to consider here. First, IMAXcontributes to the overall supply current for the circuit, soyou would generally make it as small as possible.Second, IMAXcannot be too small or leakage currents willadversely affect the programmed threshold voltages; 5µAis often appropriate. Determine R3 after you have cho-sen IMAX. Use the value for R3 to determine R2, then useboth R2 and R3 to determine R1.
For example, to program a 4.75V low-line threshold and a4.4V reset threshold, first choose IMAXto be 5µA whenVCC= 5.5V and substitute into equation 1.
R3 = (1.30 x 5.5)/(4.75 x 5E-6) = 301.05kΩ.
301kΩis the nearest standard 0.1% value. Substituteinto equation 2:
R2 = [(1.30 x 5.5)/(4.4 x 5E-6)] - 301kΩ= 23.95kΩ.The nearest 0.1% resistor value is 23.7kΩ. Finally, sub-stitute into equation 3:
R1 = (5.5/5E-6) - (23.7kΩ+ 301kΩ) = 775kΩ.
The nearest 0.1% value resistor is 787kΩ. Determine theactual low-line threshold by rearranging equation 1 andplugging in the standard resistor values. The actual low-line threshold is 4.75V and the actual reset threshold is4.40V. An additional resistor allows the MAX792/MAX820to monitor the unregulated supply and provide an NMIbefore the regulated supply begins to fall (Figure 4c).Both of these thresholds will vary from circuit to circuitwith resistor tolerance, reference variation, and compara-tor offset variation. The initial thresholds for each circuitwill also vary with temperature due to reference and off-set drift. For highest accuracy, use the MAX820.
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX820VCC3RESET IN/INT4*VCCRESETCOMPARATORRESETGENERATORVCC2RESET1RESETLLIN/REFOUT5VCCLOW-LINECOMPARATORVCCCHIP-ENABLEOUTPUTVCCP10LOW LINEMR9CONTROLMANUALRESETCOMPARATOR1.30VVCCINTERNAL/EXTERNALMODECONTROL60mVINTERNALEXTERNALPCE IN1413CE OUTTIMEBASE FORRESET ANDNWATCHDOG168WATCHDOGWDPOSWTTIMER15WDOWDI11WATCHDOGVCCTRANSITIONDETECTORMAX792OVERVOLTAGEMAX820COMPARATOR6OVOOVI712GND* SWITCHES ARE SHOWN IN INTERNALTHRESHOLD MODE POSITIONFigure 1. Block Diagram_______________________________________________________________________________________
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX820MRRESET25µs MIN12µs TYP4RESET IN/INTVIN3VCCRESET2TO µPCE IN OVCE OUT515µs TYPMAX792LLIN/REFOUTRESET1TO µPLOW LINE10TO µP NMIFigure 2. Manual-Reset Timing DiagramMANUAL RESET9**...GND12MRFigure 4a. Connection for Internal Threshold ModeMAX792MAX820R1VINOTHERRESETSOURCES3VCCRESET IN/INTRESET2TO µP*DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTSFigure 3. Diode \"OR\" connections allow multiple reset sourcesto connect to MR.R2MAX792LLIN/REFOUTRESET1TO µPLow-Line OutputIn internal threshold mode, the low-line comparatormonitors VCCwith a threshold voltage typically 120mVabove the reset threshold, and with 15mV of hysteresis.For normal operation (VCCabove the reset threshold),LOWLINEis pulled to VCC. Use LOWLINEto provide anNMI to the µP, as described in the previous section,when VCCbegins to fall (Figure 4).
R3LOW LINEGND12R3 = 1.30V x VCC MAX VLOW LINE x IMAXR2 = 1.30V x VCC MAX– R3 VRESET x IMAXR1 = VCC MAX– (R2 + R3) IMAX10TO µP NMIReset FunctionThe MAX792/MAX820 provide both RESET and RESEToutputs. The RESET and RESEToutputs ensure that theµP powers up in a known state, and prevent code-exe-cution errors during power-up, power-down, orbrownout conditions.
The reset function will be asserted during the followingconditions:
1)VCCless than the programmed reset threshold.2)MRless than 1.30V typ.
3)Reset remains asserted for 200ms typ after VCC
rises above the reset threshold or after MRhas exceeded 1.30V typ.
10
IMAX = THE MAXIMUM DESIRED CURRENT THROUGH THE VOLTAGE DIVIDED.Figure 4b. Connection for External Threshold Programming ModeWhen reset is asserted, all the internal counters arereset, the watchdog output (WDO)and watchdog-pulseoutput (WDPO)are set high, and the set watchdog-time-out input (SWT) is set to (VCC- 0.6V) if it is not alreadyconnected to VCC(for internal timeouts). The chip-enable transmission gate is also disabled while reset isasserted; the chip-enable input (CEIN) becomes highimpedance and the chip-enable output (CEOUT) ispulled up to VCC.
______________________________________________________________________________________
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX820REGULATORRESETR3R1R4VCCRESET IN/INTRESET2TO µP110kTO µP RESETMAX792MAX820MAX792MAX820LLIN/REFOUTRESET1TO µPR2LOW LINE10VLOW LINE = 1.3 R1 + R2TO µP NMIFigure 5. Adding an external pull-down resistor ensuresRESETis valid with VCCdown to GND.()GNDVOLTAGE REGULATOR R2VRESET = 1.3 R3 + R4 R4( )3VCCFigure 4c. Alternative connection for external programming modeReset Outputs (RESET and RESET)MAX792MAX820The RESEToutput is active low and typically sinks 1.6mA7OVIat 0.1V. When deasserted, RESETsources 1.6mA atOVO6OVERVOLTAGEtypically VRESETCC - 1.5V. The RESET output is the inverse ofRESET.is guaranteed to be valid down to V1V, and an external 10kΩpull-down resistor on RESETCC=1.30Vensures that it will be valid with V(Figure 5). As VCCdown to GNDRESEToutput switch reduces accordingly, increasingCCgoes below 1V, the gate drive to theGND12the rDS(ON)and the saturation voltage. The 10kΩpull-down resistor ensures that the parallel combination ofswitch plus resistor will be around 10kΩand the satura-tion voltage will be below 0.4V while sinking 40µA.Figure 6. Detecting an Overvoltage ConditionWhen using an external pull-down resistor of 10kΩ, thehigh state for the RESEToutput with VCC= 4.75V is typi-Watchdog Functioncally 4.60V.
The watchdog monitors µP activity via the watchdoginput (WDI). If the µP becomes inactive,WDOandOvervoltage ComparatorWDPOare asserted. To use the watchdog function,The overvoltage comparator is an uncommitted com-connect WDI to a µP bus line or I/O line. If WDIparator that has no effect on the operation of other chipremains high or low for longer than the watchdog time-functions. Use this input to provide overvoltage indica-out period (1.6sec nominal), WDPOand WDOare assert-tion by connecting a voltage divider from the input sup-ed, indicating a software fault condition (seeply, as in Figure 6.
Watchdog-Pulse Outputand Watchdog Outputsec-Connect OVI to ground if the overvoltage function is nottions).
used. OVOgoes low when OVI goes above 1.30V. WithOVI below 1.30V, OVOis actively pulled to VWatchdog InputCCand cansource1µA.
If the watchdog function is unused, connect WDI to Vor GND. A change of state (high-to-low, low-to-high, orCCa minimum 100ns pulse) at WDI during the watchdogperiod resets the watchdog timer. The watchdog timer
______________________________________________________________________________________
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX8201.6secWDIWDPO70nsWDOMIN 100ns (VCC = 5V)MIN 300ns (VCC = 3V)VCC3VCC0.1µFVCCµP POWER1111615VCLOCKCCQCLEARQTWOCONSECUTIVEWATCHDOGFAULTINDICATIONRESETI/OMAX792MAX820RESETWDIWDPO9MRGND12WDOVCC = 5VFigure 7. WDI, WDOand WDPOTiming Diagram+5VD*default is 1.6sec. Select alternative timeout periods byconnecting an external capacitor from SWT to GND(see Selecting an Alternative Watchdog Timeoutsec-tion). When VCCis below the reset threshold, thewatchdog function is disabled.
0.1µFREACTIVATE4.7k* FOR SYSTEM RESET ON EVERY WATCHDOG FAULT, OMIT THE FLIP-FLOP, AND DIODE–OR CONNECT WDO TO MR.Watchdog OutputWDOremains high if there is a transition or pulse at WDIduring the watchdog timeout period. The watchdogfunction is disabled and WDOis a logic high when VCCis below the reset threshold. If a system reset isdesired on every watchdog fault, simply diode-OR con-nect WDOto MR(Figure 8). When a watchdog faultoccurs in this mode, WDOgoes low, pulling MRlow andcausing a reset pulse to be issued. As soon as reset isasserted, the watchdog timer clears and WDOgoeshigh. With WDOconnected to MR, a continuous high orlow on WDI will cause 200ms reset pulses to be issuedevery 1.6sec (SWT connected to VCC). When reset isnot asserted, if no transition occurs at WDI during thewatchdog timeout period, WDOgoes low 70ns after thefalling edge of WDPOand remains low until the next tran-sition at WDI (Figure 7). A single additional flip-flop canforce the system into a hardware shutdown if there aretwo successive watchdog faults (Figure 8).When theMAX792/MAX820 are operated from a 5V supply, WDOhas a 2 x TTL output characteristic.
Watchdog-Pulse OutputAs described in the preceding section, WDPOcan beused as the clock input to an external D flip-flop. Uponthe absence of a watchdog edge or pulse at WDI at theend of a watchdog timeout period, WDPOwill pulse lowfor 1.7ms. The falling edge of WDPOprecedes WDOby70ns. Since WDOis high when WDPOgoes low, the flip-flop’s Q output remains high after WDOgoes low (Figure8). If the watchdog timer is not reset by a transition at
12
Figure 8. Two consecutive watchdog faults latch the system inreset.WDI, WDOremains low and the next WDPOfollowing asecond watchdog timeout period clocks a logic low tothe Q output, pulling MRlow and causing theMAX792/MAX820 latch in reset. If the watchdog timeris reset by a transition at WDI, WDOwill go high and theflip-flop’s Q output will remain high. Thus a systemshutdown is only caused by two successive watchdogfaults.
Selecting an Alternative Watchdog Timeout PeriodThe SWT input controls the watchdog timeout period.Connecting SWT to VCCselects the internal 1.6secwatchdog timeout period. Select an alternative watch-dog timeout period by connecting a capacitor betweenSWT and GND. Do not leave SWT floating and do notconnect it to ground. The following formula determinesthe watchdog timeout period:Watchdog Timeout Period =
k x (capacitor value in nF)ms
where k = 27 for VCC= 3V, and k = 16.2 for VCC= 5V.This applies for capacitor values in excess of 4.7nF. Ifthe watchdog function is unused, connect SWT to VCC.
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Microprocessor and Non-VolatileMemory Supervisory CircuitsChip-Enable Signal GatingThe MAX792/MAX820 provide internal gating of chip-enable (CE) signals, which prevents erroneous datafrom corrupting CMOS RAM in the event of an under-voltage condition. The MAX792/MAX820 use a seriestransmission gate from CEIN to CEOUT (Figure 1).
During normal operation (reset not asserted), the CEtransmission gate is enabled and passes all CE transi-tions. When reset is asserted, this path becomes dis-abled, preventing erroneous data from corrupting theCMOS RAM. The 10ns max CE propagation delay fromCEIN to CEOUT enables the MAX792/MAX820 to beused with most µPs. If CEIN is low when reset asserts,CEOUT remains low for a short period to permit com-pletion of the current write cycle.
VCCRESETTHRESHOLDCE INMAX792/MAX820CE OUT15µs70µs70µsRESETRESETChip-Enable InputFigure 9. Reset and Chip-Enable TimingThe CE transmission gate is disabled and CEIN is highimpedance (disabled mode) while reset is asserted.+5VDuring a power-down sequence when VCCpasses the3reset threshold, the CE transmission gate disables andVCCCEIN immediately becomes high impedance if the volt-age at CEIN is high. If CEIN is low when reset isMAX792asserted, the CE transmission gate will disable at the14MAX820moment CEIN goes high or 15µs after reset is asserted,CE INCE OUT13whichever occurs first (Figure 9). This permits the cur-50Ω DRIVERCLOADrent write cycle to complete during power-down.
During a power-up sequence, the CE transmission gateGNDremains disabled and CEIN remains high impedance12regardless of CEIN activity, until reset is deasserted fol-lowing the reset timeout period.
While disabled, CEIN is high impedance. When the CEFigure 10. CE Propagation Delay Test Circuittransmission gate is enabled, the impedance of CEINwill appear as a 75Ω(VChip-Enable OutputCEOUT.
CC= 5V) resistor in series withthe load at When the CE transmission gate is enabled, the imped-The propagation delay through the CE transmissionance of CEOUT is equivalent to 75Ωin series with thegate depends on Vsource driving CEIN. In the disabled mode, the 75Ωdrive connected to CECC,the source impedance of theIN, and the loading on CEOUTtransmission gate is off and an active pull-up connects(see the Chip-Enable Propagation Delay vs. CEOUTfrom CEOUT to VLoad Capacitance graph in the Typical Operatingtransmission gate is enabled.
CC. This source turns off when theCharacteristics). The CE propagation delay is produc-tion tested from the 50% point on CEIN to the 50%__________Applications Informationpoint on CEOUT using a 50Ωdriver and 50pF of loadConnect a 0.1µF ceramic capacitor from VCCto GND,capacitance (Figure 10). For minimum propagationas close to the device pins as possible. This reducesdelay, minimize the capacitive load at CEOUT, and usethe probability of resets due to high-frequency power-a low output impedance driver.
supply transients. In a high-noise environment, addi-tional bypass capacitance from VCCto ground may berequired. If long leads connect to the chip inputs,ensure that these lines are free from ringing, etc., whichwould forward bias the chip’s protection diodes.
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX820+5V3VCCRP*CERAM 1CECE13RAM 2CECEGND12RAM 3CECE*MAXIMUM RP VALUE DEPENDS ONTHE NUMBER OF RAMS.MINIMUM RP VALUE IS 1kΩRAM 4CEACTIVE-HIGH CELINES FROM LOGICVCC3VCCRESET14.7kRESETVCCµPBUFFERTO OTHER SYSTEM RESETINPUTS14MAX792MAX820CE INCE OUTMAX792MAX820GND12GNDFigure 11. Alternate CE GatingFigure 12. Interfacing to µPs with Bidirectional RESETPinsAlternative Chip-Enable GatingUsing memory devices with both CE and CEinputsallows the MAX792/MAX820 CE propagation delayto be bypassed. To do this, connect CEIN to ground,pull up CEOUT to VCC, and connect CEOUT to the CEinput of each memory device (Figure 11). The CE inputof each memory device then connects directly to thechip-select logic, which does not have to be gated bythe MAX792/MAX820.
Interfacing to µPs with Bidirectional Reset InputsµPs with bidirectional reset pins, such as the Motorola68HC11 series, can contend with the MAX792/MAX820RESEToutput. If, for example, the MAX792/MAX820RESEToutput is asserted high and the µP wants to pull itlow, indeterminate logic levels may result. To avoidthis, connect a 4.7kΩresistor between theMAX792/MAX820 RESEToutput and the µP reset I/O, asin Figure 12. Buffer the MAX792/MAX820 RESEToutputto other system components.
going VCCpulses, starting at 5V and ending below thereset threshold by the magnitude indicated (reset-comparator overdrive). The graph shows the maximumpulse width a negative-going VCCtransient may typi-cally have without causing a reset pulse to be issued.As the amplitude of the transient increases (i.e., goesfarther below the reset threshold), the maximum allow-able pulse width decreases. Typically, a VCCtransientthat goes 100mV below the reset threshold and lasts for30µs or less will not cause a reset pulse to be issued.A 100nF bypass capacitor mounted close to the VCCpin provides additional transient immunity.
MAXIMUM TRANSIENT DURATION (µs)8060VCC = 5VTA = +25°CNegative-Going VCCTransientsWhile issuing resets to the µP during power-up, power-down, and brownout conditions, these supervisors arerelatively immune to short-duration negative-going VCCtransients (glitches). It is usually undesirable to resetthe µP when VCCexperiences only small glitches.
Figure 13 shows maximum transient duration vs. reset-comparator overdrive, for which reset pulses are notgenerated. The graph was produced using negative-14
4020010100100010,000RESET COMPARATOR OVERDRIVE, (VTH - VCC) (mV)Figure 13. Maximum Transient Duration without Causing aReset Pulse vs. Reset-Comparator Overdrive______________________________________________________________________________________MAX791 -13100元器件交易网www.cecb2b.com
Microprocessor and Non-VolatileMemory Supervisory Circuits_Ordering Information (continued)PART**MAX792_EPEMAX792_ESEMAX792_EJEMAX792_MJEMAX820_CPEMAX820_CSEMAX820_EPEMAX820_ESEMAX820_EJEMAX820_MJE
TEMP. RANGE-40°C to +85°C-40°C to +85°C-40°C to +85°C-55°C to +125°C-0°C to +70°C-0°C to +70°C-40°C to +85°C-40°C to +85°C-40°C to +85°C-55°C to +125°C
PIN-PACKAGE16 Plastic DIP16 Narrow SO16 CERDIP16 CERDIP16 Plastic DIP16 Narrow SO16 Plastic DIP16 Narrow SO16 CERDIP16 CERDIP
__________________Pin ConfigurationTOP VIEWRESET1RESET2VCC3RESET IN/INT4LLIN/REFOUT5OVO6OVI7SWT816WDPO15WDOMAX792/MAX820MAX792MAX82014CE IN13CE OUT12GND11WDI10LOW LINE9MR* Dice are tested at TA= +25°C.**These parts offer a choice of five different reset threshold volt-DIP/SOages. Select the letter corresponding to the desired nominalreset threshold voltage and insert it into the blank to completethe part number.___________________Chip TopographySUFFIXRESET THRESHOLD (V)
ML4.62T4.37S3.06RESETWDOR
2.91RESETWDPOCE IN2.61
VCC
CE OUT RESET IN/
INT LLIN/GND.078\"(1.981mm)REF OUT
OVO
WDIOVISWTMRLOWLINE.070\"(1.778mm)TRANSISTOR COUNT: 950;SUBSTRATE CONNECTED TO VCC.
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Microprocessor and Non-VolatileMemory Supervisory CircuitsMAX792/MAX820________________________________________________________Package InformationD1DIMAA1A2A3BB1CDD1EE1eeAeBLαINCHESMINMAX–0.2000.015–0.1250.1500.0550.0800.0160.0220.0500.0650.0080.0120.7450.7650.0050.0300.3000.3250.2400.2800.100 BSC0.300 BSC–0.4000.1150.1500˚15˚MILLIMETERSMINMAX–5.080.38–3.183.811.402.030.410.561.271.650.200.3018.9219.430.130.767.628.266.107.112.54 BSC7.62 BSC–10.162.923.810˚15˚21-587AEDA3AA2E1LA1eBαCB1eAeB16-PIN PLASTICDUAL-IN-LINEPACKAGEEHDIMAA1BCDEeHhLαINCHESMAXMIN0.0690.0530.0100.0040.0190.0140.0100.0070.3940.3860.1570.1500.050 BSC0.2440.2280.0200.0100.0500.0168˚0˚MILLIMETERSMINMAX1.351.750.100.250.350.490.190.259.8010.003.804.001.27 BSC5.806.200.250.500.401.270˚8˚21-588BDAeB0.127mm0.004in.h x 45˚αA1CL16-PIN PLASTICSMALL-OUTLINE(NARROW)PACKAGEMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.16____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600Printed USA
is a registered trademark of Maxim Integrated Products.
©1994 Maxim Integrated Products
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