19-2100; Rev 0; 8/01
Quad Bus LVDS Driver with
Flow-Through Pinout
General Description
FeaturesThe MAX9129 is a quad bus low-voltage differential sig-naling (BLVDS) driver with flow-through pinout. ThisoDrive LVDS Levels into a 27ΩLoaddevice is designed to drive a heavily loaded multipointo1ns (0% to 100%) Minimum Transition Timebus with controlled transition times (1ns 0% to 100%Reduces Reflectionsminimum) for reduced reflections. The MAX9129accepts four LVTTL/LVCMOS input levels and trans-oGuaranteed 200Mbps (100MHz) Data Ratelates them to output levels of 250mV to 450mV (stan-oEnable Pins for High-Impedance Outputdard LVDS levels) into a 27Ωload at speeds up to200Mbps (100MHz).
oHigh-Impedance Outputs when Powered OffThe power-on reset ensures that all four outputs areoGlitch-Free Power-Up and Power-Downdisabled and high impedance during power up andpower down. The outputs can be set to high imped-oHot Swappableance by two enable inputs, EN and EN, thus droppingoFlow-Through Pinout
the device to a low-power state of 11mW. The enablesare common to all four drivers. The flow-through pinoutoAvailable in Tiny QFN Package (50% Smaller simplifies PC board layout and reduces crosstalk bythan TSSOP)keeping the LVTTL/LVCMOS inputs and BLVDS outputsoSingle +3.3V Supply
separated.
The MAX9129 operates from a single +3.3V supply andis specified for operation from -40°C to +85°C. It isavailable in 16-pin QFN and TSSOP packages. Refer tothe MAX9121 data sheet for a quad LVDS line receiverOrdering Information
with flow-through pinout.
PARTTEMP. RANGEPIN-PACKAGEApplications
MAX9129EGE-40°C to +85°C16 QFNMAX9129EUE-40°C to +85°C16 TSSOPCell Phone Base StationsAdd/Drop Muxes Digital Cross-ConnectsFunctional Diagram appears at end of data sheet.DSLAMs
Pin Configurations appear at end of data sheet.
Network Switches/RoutersBackplane InterconnectClock Distribution
Typical Applications Circuit
CARD 1ACARD 10ACARD 1BCARD 2BMAX9129MAX9121MAX9129MAX9121MAX9129MAX9121MAX9129MAX9121BUS ARtBUS BRt= TERMINATIONRtMULTIPOINT FULL-DUPLEX TRANSMIT AND RECEIVE BUSRtR RESISTORt________________________________________________________________Maxim Integrated Products1
For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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Quad Bus LVDS Driver with Flow-Through PinoutMAX9129ABSOLUTE MAXIMUM RATINGS
VCCto GND...........................................................-0.3V to +4.0VIN_, EN, ENto GND....................................-0.3V to (VCC+ 0.3V)OUT_+, OUT_- to GND..........................................-0.3V to +4.0VShort-Circuit Duration (OUT_+, OUT_-).....................ContinuousContinuous Power Dissipation (TA= +70°C)
16-Pin QFN (derate 18.5mW/°C above +70°C).........1481mW 16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
Storage Temperature Range.............................-65°C to +150°CMaximum Junction Temperature.....................................+150°COperating Temperature Range...........................-40°C to +85°CESD Protection
Human Body Model, OUT_+, OUT_-...............................±8kVLead Temperature (soldering, 10s).................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 27Ω±1%, EN = high, EN= low, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Notes 1, 2)PARAMETERDifferential Output VoltageChange in Magnitude of VODBetween Complementary OutputStatesOffset VoltageChange in Magnitude of VOSBetween Complementary OutputStatesOutput High VoltageOutput Low VoltageDifferential Output Short-CircuitCurrentOutput Short-Circuit CurrentOutput High-Impedance CurrentPower-Off Output CurrentOutput CapacitanceINPUTS (IN_, EN, EN)High-Level Input VoltageLow-Level Input VoltageInput Current SUPPLY CURRENTSupply CurrentDisabled Supply CurrentICCICCZRL = 27Ω, IN_ = VCC or 0 for all channelsDisabled583.2705mAmAVIHVILIININ_, EN, EN = 0 or VCC2.0GND-15VCC0.815VVµASYMBOLVOD∆VODVOS∆VOSVOHVOLIOSDIOSIOZIOFFCOUTVOD = 0OUT_+ = 0 at IN_ = VCC orOUT_- = 0 at IN_ = 0Disabled, OUT_+ = 0 or VCC, OUT_- = 0or VCCVCC = 0 or open, EN = EN = IN_ = 0,OUT_+ = 0 or 3.6V, OUT_- = 0 or 3.6V-1-10.90Figure 1Figure 1Figure 1Figure 11.125CONDITIONSMIN250TYP37111.2951.4651.08520-2011MAX450251.375251.6UNITSmVmVVmVVVmAmAµAµApFBLVDS OUTPUTS (OUT_+, OUT_-)C ap aci tance fr om OU T_+ or O UT _- to G ND 4.32_______________________________________________________________________________________
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Quad Bus LVDS Driver with
Flow-Through Pinout
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, RL= 27Ω±1%, CL= 15pF, EN = high, EN= low, TA= -40°C to +85°C, unless otherwise noted. Typical valuesare at VCC= +3.3V, TA= +25°C.) (Notes 3, 4, 5)PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential Propagation DelayHigh to LowtPHLDFigures 2 and 31.01.983.0nsDifferential Propagation DelayLow to HightPLHDFigures 2 and 31.01.923.0nsDifferential Pulse Skew (Note 6)tSKD1Figures 2 and 3300psDifferential Channel-to-ChannelSkew (Note 7)tSKD2Figures 2 and 3450psDifferential Part-to-Part Skew(Note 8)tSKD3Figures 2 and 31.2nsDifferential Part-to-Part Skew(Note 9)tSKD4Figures 2 and 32.0nsRise TimetMAX9129EGE0.601.191.55TLHFigures 2 and 3MAX9129EUE0.601.091.40nsFall TimetMAX9129EGE0.601.121.55THLFigures 2 and 3MAX9129EUE0.601.021.40nsDisable Time High to ZtPHZFigures 4 and 58nsDisable Time Low to ZtPLZFigures 4 and 58nsEnable Time Z to HightPZHFigures 4 and 510nsEnable Time Z to LowtPZLFigures 4 and 510nsMaximum Operating Frequency(Note 10)fMAXFigure 2100MHzNote 1:Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at TA= +25°C.
Note 2:Current into the device is defined as positive, and current out of the device is defined as negative. All voltages are
referenced to ground except VODand ∆VOD.
Note 3:AC parameters are guaranteed by design and characterization.Note 4:CLincludes probe and jig capacitance.
Note 5:Signal generator conditions: VOL= 0, VOH= VCC, f = 100MHz, 50% duty cycle, RO= 50Ω, tR= tF= 1ns (10% to 90%).Note 6:tSKD1is the magnitude difference of differential propagation delays. tSKD1= | tPHLD- tPLHD |.
Note 7:tSKD2is the magnitude difference of tPHLDor tPLHDof one channel to the tPHLDor tPLHDof another channel on the
same device.
Note 8:tSKD3is the magnitude difference of any differential propagation delays between devices at the same VCCand within 5°C
of each other.
Note 9:tSKD4is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 10:Signal generator conditions: VOL= 0, VOH= VCC, f = 100MHz, 50% duty cycle, R≥250mV, all channels switching.
O= 50Ω, tR= tF= 1ns (10% to 90%).
MAX9129 output criteria: duty cycle = 45% to 55%, VOD_______________________________________________________________________________________3
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Quad Bus LVDS Driver with Flow-Through PinoutMAX9129Typical Operating Characteristics(MAX9129EUE (TSSOP package), VCC= +3.3V, RL= 27Ω, CL = 15pF, TA= +25°C, unless otherwise noted.) (Note 5)
OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
MAX9129 toc02MAX9129 toc01OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
1.48
1.12
OUTPUT SHORT CURRENT (IOS)
vs. SUPPLY VOLTAGE
MAX9129 toc03-14.12OUTPUT SHORT CURRENT (mA)OUTPUT HIGH VOLTAGE (V)OUTPUT LOW VOLTAGE (V)1.47
1.10-14.11
1.46
1.08-14.10
1.45
1.06-14.09
1.44
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
1.04
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
-14.08
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
OUTPUT HIGH-IMPEDANCE CURRENT
vs. SUPPLY VOLTAGE
MAX9129 toc04DIFFERENTIAL OUTPUT VOLTAGE vs.
SUPPLY VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE (mV)MAX9129 toc05DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTANCE
MAX9129 toc06430OUTPUT HIGH-IMPEDANCE CURRENT (pA)VOUT_ = VCC OR 0428
372.01.750DIFFERENTIAL OUTPUT VOLTAGE (V)1.5001.2501.0000.7500.5000.250
0
371.5
426
371.0
424
422
370.5
420
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
370.0
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
1030507090110130150
LOAD RESISTANCE (Ω)
OUTPUT OFFSET VOLTAGEvs. SUPPLY VOLTAGE
MAX9129 toc07SUPPLY CURRENT vs. FREQUENCY
MAX9129 toc08SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9129 toc091.3051.300OUTPUT OFFSET VOLTAGE (V)1.2951.2901.2851.2801.2751.2701.265
3.0
3.3
SUPPLY VOLTAGE (V)
65
57.7
63SUPPLY CURRENT (mA)57.5SUPPLY CURRENT (mA)61
57.3
59
57.1
57
56.9
55
3.6
0
1
100
FREQUENCY (MHz)
10
1000
56.7
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
4_______________________________________________________________________________________
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Quad Bus LVDS Driver with
Flow-Through Pinout
Typical Operating Characteristics (continued)(MAX9129EUE (TSSOP package), VCC= +3.3V, RL= 27Ω, CL = 15pF, TA= +25°C, unless otherwise noted.) (Note 5)
SUPPLY CURRENT vs. TEMPERATURE
DIFFERENTIAL PROPAGAION DELAY
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
60
012.1012.2021c1cocoto ))t 9t 2s9s91n2n2191((9X9 59AYXMAYXAA2.05MA2.10MLLEt)PHLDAEmDD t (N NPHLDTO2.00O2.00NIITE58
TARAGRGUAAPCPO O1.951.90YRRLPPP57
LPLtAUAIIT1.90T1.80PLHDSNNEtPLHDE56
RREEF1.85FFF1.70IIDD55-40
-15
10
35
6085
1.80
1.60
3.0
3.3
3.6
-40-1510356085
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL SKEWvs. SUPPLY VOLTAGE
DIFFERENTIAL SKEWTRANSITION TIMEvs. TEMPERATURE
vs. SUPPLY VOLTAGE
703110041.3
51c1cocotot t 9 9291220% TO 80%260911X99AXXMAM)801.2AMs)ps)tpsTLH( 50( nWW( EEEKKMSS60I1.1
TL40 ALANITIOTINNTEIR30ESER40N1.0
FEAFFRITD20FIDtTHL1020
0.9
00.83.0
3.3
3.6
0-40
-15
10
35
6085
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TRANSITION TIMEvs. TEMPERATURE
1.250
6120% TO 80%cot 1.2009219X1.150tATLHM)sn( E1.100MIT N1.050OITIS1.000NART0.950tTHL0.9000.8500.800
-40
-15
10
35
60
85
TEMPERATURE(°C)
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Quad Bus LVDS Driver with Flow-Through PinoutMAX9129Pin DescriptionPINQFN151, 4, 5, 162367, 10, 11, 148, 9, 12, 13TSSOP12, 3, 6, 74589, 12, 13, 1610, 11, 14, 15NAMEFUNCTIONLVTTL/LVCMOS Enable Input. The driver is disabled when EN is low. EN is internallypulled down. When EN = high and EN = low or open, the outputs are active. For othercombinations of EN and EN, the outputs are disabled and are high impedance.LVTTL/LVCMOS Driver InputsPower-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors.GroundLVTTL/LVCMOS Enable Input. The driver is disabled when EN is high. EN is internallypulled down.Inverting BLVDS Driver OutputsNoninverting BLVDS Driver OutputsENIN_VCCGNDENOUT_-OUT_+OUT_+CLOUT_ +VOSVODSRL/2VCCGNDRL/2IN_GENERATORIN_RLVO50ΩCLOUT_ -OUT_-Figure 1. Driver VODand VOSTest Circuit
Figure 2. Driver Propagation Delay and Transition Time TestCircuit
VCCIN_50%50%0tPLHDOUT_ -0 DIFFERENTIALOUT_+0VOL80%0VOD20%tTLHtTHL80%VOD = (VOUT_+) - (VOUT_-)020%tPHLDVOHFigure 3. Driver Propagation Delay and Transition Time Waveforms
6_______________________________________________________________________________________
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Quad Bus LVDS Driver with
Flow-Through Pinout
CLTable 1. Input/Output Function TableENABLESINPUTSOUTPUTSOUT_+ENENIN_OUT_+OUT_ -VCCIN_RL/2HL or openLLHGNDHHLEN+1.2VAll other combinations ofEN and ENXZZGENERATORENRL/250ΩOUT_-1/4 MAX9129CLFigure 4. Driver High-Impedance Delay Test Circuit
EN WHEN EN = 0 OR OPENVCC50%50%0VCC50%50%EN WHEN EN = VCC0tPHZtPZHOUT_+ WHEN IN_ = VCCOUT_- WHEN IN_ = 0VOH50%50%1.2V1.2V50%50%OUT_+ WHEN IN_ = 0OUT_- WHEN IN_ = VVCCOLtPLZtPZLFigure 5. Driver High-Impedance Delay Waveform
Detailed Descriptionas the MAX9121, to implement full-duplex multipointThe MAX9129 is a 200Mbps quad differential BLVDSbuses more efficiently than with transceivers.
driver designed for multipoint, heavily loaded backplaneapplications. This device accepts LVTTL/LVCMOS inputEffect of Capacitive Loading
levels and translates them to output levels of 250mV toThe characteristic impedance of a differential PC board450mV into a 27Ωload. The flow-through pinout simpli-trace is uniformly reduced when equal capacitive loadsfies board layout and reduces the potential for crosstalkare attached at equal intervals (provided the transitionbetween single-ended inputs and differential outputs.time of the signal being driven on the trace is longerTransition times are designed to reduce reflections, yetthan the delay between loads). This kind of loading isenable high data rates. The MAX9129 can be used intypical of multipoint buses where cards are attached atconjunction with standard quad LVDS receivers, such
1in or 0.8in intervals along the length of a backplane.
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Quad Bus LVDS Driver with Flow-Through PinoutMAX9129The reduction in characteristic impedance is approxi-mated by the following formula:
ZDIFF-loaded= ZDIFF-unloaded✕SQRT [Co/ (Co+ N ✕CL/ L)]where:
ZDIFF-unloaded= unloaded differential characteristic im-pedance
Co= unloaded trace capacitance (pF/unit length)CL= value of each capacitive load (pF)N = number of capacitive loads
L = trace length
For example, if Co= 2.5pF/in, CL= 10pF, N = 18, L =18in, and ZDIFF-unloaded= 120Ω, the loaded differentialimpedance is:
ZDIFF-loaded= 120Ω✕SQRT [2.5pF / (2.5pF + 18 ✕10pF/18in)]
ZDIFF-loaded= 54Ω
In this example, capacitive loading reduces the charac-teristic impedance from 120Ωto 54Ω. The load seen bya driver located on a card in the middle of the bus is27Ωbecause the driver sees two 54Ωloads in parallel.A typical LVDS driver (rated for a 100Ωload) would notdevelop a large enough differential signal to be reliablydetected by an LVDS receiver. Maxim’s BLVDS driver isdesigned and specified to drive a 27Ωload to differen-tial voltage levels of 250mV to 450mV (which are stan-dard LVDS driver levels). A standard LVDS receiver isable to detect this level of differential signal.
Short extensions off the bus, called stubs, contribute tocapacitive loading. Keep stubs less than 1in for a goodbalance between ease of component placement andgood signal integrity.
The MAX9129 is a current source driver and driveslarger differential signal levels into loads higher than27Ωand smaller levels into loads less than 27Ω(seetypical operating curves). To keep loading from reduc-ing bus impedance below the rated 27Ωload, PCboard traces can be designed for higher unloadedcharacteristic impedance.
minimum transition time of 1ns (rated 0.6ns from 20% to80%, or about 1ns 0% to 100%) to reduce reflectionswhile being fast enough for high-speed backplane datatransmission.
Power-On Reset
The power-on reset voltage of the MAX9129 is typically2.25V. When the supply falls below this voltage, thedevice is disabled and the outputs are in high imped-ance.
Applications Information
Power-Supply Bypassing
Bypass VCCwith high-frequency, surface-mountceramic 0.1µF and 0.001µF capacitors in parallel asclose to the device as possible, with the smaller valuedcapacitor closest to VCC.
Termination
In the example above, the loaded differential imped-ance of the bus is reduced to 54Ω. Since it can be dri-ven from any card position, the bus must be terminatedat each end. A parallel termination of 54Ωat each endof the bus placed across the traces that make up thedifferential pair provides a proper termination. The totalload seen by the driver is 27Ω.
The MAX9129 drives higher differential signal levelsinto lighter loads. A multidrop bus with the driver at oneend and receivers connected at regular intervals alongthe bus has a lowered impedance due to capacitiveloading. Assuming the same impedance calculated inthe multidrop example above (54Ω), the multidrop buscan be terminated with a single, parallel-connected54Ωresistor at the far end from the driver. Only a singleresistor is required because the driver sees one 54Ωdifferential trace. The signal swing is larger with a 54Ωload.
In general, parallel terminate each end of the bus with aresistor matching the differential impedance of the bus(taking into account any reduced impedance due toloading).
Board Layout
A four-layer PC board that provides separate power,ground, input, and output signals is recommended.Keep the LVTTL/LVCMOS and BLVDS signals separat-ed to prevent coupling as shown in the suggested lay-out for the QFN package (not drawn to scale) (Figure 6).
Effect of Transition Time
For transition times (measured from 0% to 100%) short-er than the delay between capacitive loads, the loadsare seen as low-impedance discontinuities from whichthe driven signal is reflected. Reflections add and sub-tract from the signal being driven and cause decreasednoise margin and jitter. The MAX9129 is designed for a
8
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Quad Bus LVDS Driver with
Flow-Through Pinout
ENOUT1-IN1OUT1+GNDIN2OUT2+VCCOUT2-GNDOUT3-IN3OUT3+IN4OUT4+ENOUT4-Figure 6. Suggested Layout for QFNPackage
Chip InformationTRANSISTOR COUNT: 948PROCESS: CMOS
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Quad Bus LVDS Driver with Flow-Through PinoutMAX9129Pin Configurations
TOP VIEWIN116EN1IN12IN23VCC4GND5IN36IN47EN816OUT1-15OUT1+14OUT2+IN2VCCGNDIN312345768ENOUT1-OUT1+151413GNDGND1211OUT2+OUT2-OUT3-OUT3+GNDMAX912913OUT2-12OUT3-11OUT3+10OUT4+9OUT4-MAX9129109GNDGNDIN4ENOUT4-OUT4+TSSOPQFN(4mm x 4mm)(CONTACTS UNDER QFN)Functional Diagram
OUT1+IN1OUT1-OUT2+IN2OUT2-OUT3+IN3OUT3-OUT4+IN4OUT4-ENMAX9129EN10______________________________________________________________________________________
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Quad Bus LVDS Driver with
Flow-Through Pinout
Package Information
SPE.SDAP ON,POSST______________________________________________________________________________________11
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Quad Bus LVDS Driver with Flow-Through Pinout9219XAM12Package Information (continued)
SPE.NFQ L42 ,02,61 ,21______________________________________________________________________________________
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Quad Bus LVDS Driver with
Flow-Through Pinout
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________13©2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX9129
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