M41T11
512 bit (64b x8) Serial Access TIMEKEEPER® SRAM
ss
2.0V to 5.5V SUPPLY VOLTAGE
COUNTERS for SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS and CENTURY
YEAR 2000 COMPLIANT
SOFTWARE CLOCK CALIBRATION
AUTOMATIC SWITCH-OVER and DESELECT CIRCUITRY
I2C BUS COMPATIBLE
56 BYTES of GENERAL PURPOSE RAMULTRA-LOW BATTERY SUPPLY CURRENTof 1µA
LOW OPERATING CURRENT of 300µAOPERATING TEMPERATURE of –40 to 85°CAUTOMATIC LEAP YEAR COMPENSATIONSPECIAL SOFTWARE PROGRAMMABLE OUTPUT
PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately)
VCCVBATSNAPHAT (SH)Battery & Crystalsss
81SO8 (M)150mil Widthsss
281SOH28 (MH)ssss
Figure 1. Logic Diagrams
Table 1. Signal Names
OSCIOCSOFT/OUTSDASCLVBATVCCVSS
Oscillator InputOscillator Output
Frequency Test / Output Driver (Open drain)
Serial Data Address Input / OutputSerial Clock
Battery Supply VoltageSupply VoltageGround
OSCISCLM41T11OSCOSDAFT/OUTVSSAI01000May 20001/19
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M41T11
Figure 2A. SO8 ConnectionsFigure 2B. SOH28 ConnectionsM41T11OSCIOSCOVBATVSS12348765AI01001VCCFT/OUTSCLSDADESCRIPTION
The M41T11 TIMEKEEPER® RAM is a low power512 bit static CMOS RAM organized as 64 wordsby 8 bits. A built-in 32.768 kHz oscillator (externalcrystal controlled) and the first 8 bytes of the RAMare used for the clock/calendar function and areconfigured in binary coded decimal (BCD) format.Addresses and data are transferred serially via atwo-line bi-directional bus. The built-in addressregister is incremented automatically after eachwrite or read data byte.
The M41T11 clock has a built-in power sense cir-cuit which detects power failures and automatical-ly switches to the battery supply during powerfailures. The energy needed to sustain the RAMand clock operations can be supplied from a smalllithium coin cell.
Typical data retention time is in excess of 5 yearswith a 50mA/h 3V lithium cell. The M41T11 is sup-plied in 8 lead Plastic Small Outline package or 28lead SNAPHAT package.
The 28 pin 330mil SOIC provides sockets withgold plated contacts at both ends for direct con-nection to a separate SNAPHAT housing contain-
NCNCNCNCNCNCNCNCNCNCNCNCNCVSS128272263254245236227M41T1121820919101811171216131514AI03606VCCNCFT/OUTNCNCNCNCNCSCLNCNCNCSDANCing the battery and crystal. The unique designallows the SNAPHAT battery package to bemounted on top of the SOIC package after thecompletion of the surface mount process. Inser-tion of the SNAPHAT housing after reflow pre-vents potential battery and crystal damage due tothe high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to pre-vent reverse insertion. The SOIC and battery/crys-tal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form.
For the 28 lead SOIC, the battery/crystal package(i.e. SNAPHAT) part number is \"M4Txx-BR12SHx\".
Caution: Do not place the SNAPHAT battery/crys-tal package \"M4Txx-BR12SHx\" in conductivefoam since this will drain the lithium button-cellbattery.
2/19
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M41T11
Table 2. Absolute Maximum Ratings (1)
SymbolTATSTGTSLD (2)VIOVCCIOPD
Parameter
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)Lead Solder Temperature for 10 secondsInput or Output VoltagesSupply VoltageOutput CurrentPower Dissipation
SNAPHATSOIC
Value–40 to 85–40 to 85–55 to 125
260–0.3 to 7–0.3 to 7200.25
Unit°C°C°CVVmAW
Note:1.Stresses greater than those listed under \"Absolute Maximum Ratings\" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sectionof this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affectreliability.
2.Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.OPERATION
The M41T11 clock operates as a slave device onthe serial bus. Access is obtained by implementinga start condition followed by the correct slave ad-dress (D0h). The 64 bytes contained in the devicecan then be accessed sequentially in the followingorder:1.Seconds Register2.Minutes Register3.Century/Hours Register4.Day Register5.Date Register6.Month Register7.Years Register8.Control Register9 to 64.RAM
The M41T11 clock continually monitors VCC for anout of tolerance condition. Should VCC fall belowVSO, the device terminates an access in progressand resets the device address counter. Inputs tothe device will not be recognized at this time toprevent erroneous data from being written to thedevice from an out of tolerance system. When VCCfalls below VSO, the device automatically switchesover to the battery and powers down into an ultralow current mode of operation to conserve batterylife. Upon power-up, the device switches from bat-tery to VCC at VSO and recognizes inputs.
3/19
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M41T11
Figure 3. Block Diagram1 HzOSCIOSCOFT/OUTVCCVSSVBATVOLTAGESENSEandSWITCHCIRCUITRYOSCILLATOR32.768 kHzDIVIDERSECONDSMINUTESCENTURY/HOURSDAYDATEMONTHYEARCONTROLCONTROLLOGICSCLSERIALBUSINTERFACERAM(56 x 8)ADDRESSREGISTERSDAAI02566Table 3. Register Map
Address
01234567
OUT
Data
D7STXCEB (1)
XXX
CBXXXD6
D510 Seconds10 Minutes
10 HoursX10 DateX
10 M.X
X
DateMonthYears
Calibration
D4
D3
D2
D1
D0
Function/RangeBCD FormatSecondsMinutesCentury/Hour
DayDateMonthYearControl
00-5900-590-1/00-2301-0701-3101-1200-99
SecondsMinutesHours
Day
10 YearsFT
S
Note:1.When CEB is set to ’1’, CB will toggle from ’0’ to ’1’ or from ’1’ to ’0’ every 100 years (dependent upon the initial value set).
When CEB is set to ’0’, CB will not toggle.Keys:
S = SIGN Bit;
FT = FREQUENCY TEST Bit;ST = STOP Bit;
OUT = Output level;
X = Don’t care;
CEB = Century Enable Bit;CB = Century Bit.
4/19
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M41T11
Table 4. AC Measurement Conditions
Input Rise and Fall TimesInput Pulse Voltages
Input and Output Timing Ref. Voltages
≤ 5ns
0.2VCC to 0.8VCC0.3VCC to 0.7VCC
0.8VCC0.7VCC0.3VCCAI02568Figure 4. AC Testing Load CircuitNote that Output Hi-Z is defined as the point where data is no longerdriven.
0.2VCC2-WIRE BUS CHARACTERISTICS
This bus is intended for communication betweendifferent ICs. It consists of two lines: one bi-direc-tional for data signals (SDA) and one for clock sig-nals (SCL). Both the SDA and the SCL lines mustbe connected to a positive supply voltage via apull-up resistor.
The following protocol has been defined:
–Data transfer may be initiated only when the busis not busy.
–During data transfer, the data line must remainstable whenever the clock line is High.
–Changes in the data line while the clock line isHigh will be interpreted as control signals.
Accordingly, the following bus conditions havebeen defined:
Bus not busy.Both data and clock lines remainHigh.
Start data transfer.A change in the state of thedata line, from High to Low, while the clock is High,defines the START condition.
Stop data transfer.A change in the state of thedata line, from Low to High, while the clock is High,defines the STOP condition.Table 5. Capacitance (1, 2) (TA = 25 °C, f = MHz)
SymbolCINCOUT (3)tLP
Input Capacitance (SCL)
Output Capacitance (SDA, FT/OUT)
Parameter
Data valid.The state of the data line representsvalid data when after a start condition, the data lineis stable for the duration of the High period of theclock signal. The data on the line may be changedduring the Low period of the clock signal. There isone clock pulse per bit of data.
Each data transfer is initiated with a start conditionand terminated with a stop condition. The numberof data bytes transferred between the start andstop conditions is not limited. The information istransmitted byte-wide and each receiver acknowl-edges with a ninth bit.
By definition, a device that gives out a message iscalled \"transmitterhe message is called \"receiver\". The device thatcontrols the message is called \"master\". The de-vices that are controlled by the master are called\"slaves\".
MinMax710
UnitpFpFns
Low-pass filter input time constant (SDA and SCL)2501000
Note:1.Effective capacitance measured with power supply at 5V.
2.Sampled, not 100% tested.3.Outputs deselected.
5/19
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M41T11
Table 6. DC Characteristics
(TA = –40 to 85 °C; VCC = 2.0V to 5.5V)
SymbolILIILOICC1ICC2VILVIHVOLVBAT (1)IBAT
Parameter
Input Leakage CurrentOutput Leakage CurrentSupply Current
Supply Current (Standby)Input Low VoltageInput High VoltageOutput Low VoltageBattery Supply VoltageBattery Supply Current
TA = 25°C, VCC = 0V, Oscillator ON, VBAT = 3V
IOL = 3mA
2
30.8
Test Condition0V ≤ VIN ≤ VCC0V ≤ VOUT ≤ VCC
Switch Frequency = 100kHzSCL, SDA = VCC – 0.3V
–0.30.7VCCMin
Typ
Max±1±1300700.3VCCVCC + 0.8
0.43.51
UnitµAµAµAµAVVVVµA
Note:1.STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
Table 7. Power Down/Up Trip Points DC Characteristics (1)(TA = –40 to 85 °C)
SymbolVSO (2)
Parameter
Battery Back-up Switchover Voltage
MinVBAT –0.70
TypVBAT –0.50
MaxVBAT –0.30
UnitV
Note:1.All voltages referenced to VSS.
2.Switch-over and deselect point.
Table 8. Crystal Electrical Characteristics(Externally Supplied if using the SO8 package)
SymbolfORSCL
Parameter
Resonant FrequencySeries ResistanceLoad Capacitance
12.5
Min
Typ32.768
35Max
UnitkHzkΩpF
Note:Load capacitors are integrated within the M41T11. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
STMicroelectronics recommends the KDS DT-38 Tuning Fork Type quartz crystal for industrial temperature operations.KDS can be contacted at 913-491-6825 or http://www.kdsj.co.jp for further information on this crystal type.All SNAPHAT battery/crystal tops meet these specifications.
6/19
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M41T11
Table 9. Power Down/Up AC Characteristics (1)(TA = –40 to 85 °C)
SymboltPDtREC
Parameter
SCL and SDA at VIH before Power DownSCL and SDA at VIH after Power Up
Min010
Max
Unitnsµs
Note:1.VCC fall time should not exceed 5mV/µs.
Figure 5. Power Down/Up Mode AC WaveformsVCCVSO tPDSDASCLDON'T CAREAI00596tRECAcknowledge.Each byte of eight bits is followedby one acknowledge bit. This acknowledge bit is alow level put on the bus by the receiver, whereasthe master generates an extra acknowledge relat-ed clock pulse.
A slave receiver which is addressed is obliged togenerate an acknowledge after the reception ofeach byte. Also, a master receiver must generatean acknowledge after the reception of each bytethat has been clocked out of the slave transmitter.
The device that acknowledges has to pull downthe SDA line during the acknowledge clock pulsein such a way that the SDA line is a stable Low dur-ing the High period of the acknowledge relatedclock pulse. Of course, setup and hold times mustbe taken into account. A master receiver must sig-nal an end-of-data to the slave transmitter by notgenerating an acknowledge on the last byte thathas been clocked out of the slave. In this case, thetransmitter must leave the data line High to enablethe master to generate the STOP condition.
7/19
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M41T11
Table 10. AC Characteristics
(TA = –40 to 85 °C; VCC = 2.0V to 5.5V)
SymbolfSCLtLOWtHIGHtRtFtHD:STAtSU:STAtSU:DATtHD:DAT (1)tSU:STOtBUF
SCL Clock FrequencyClock Low PeriodClock High PeriodSDA and SCL Rise TimeSDA and SCL Fall Time
START Condition Hold Time
(after this period the first clock pulse is generated)START Condition Setup Time
(only relevant for a repeated start condition)Data Setup TimeData Hold Time
STOP Condition Setup Time
Time the bus must be free before a new transmission can start
44.725004.74.7
Parameter
Min04.74
1300Max100
UnitkHzµsµsµsnsµsµsnsµsµsµs
Note:1.Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
WRITE MODE
In this mode the master transmitter transmits tothe M41T11 slave receiver. Bus protocol is shownin Figure 10. Following the START condition andslave address, a logic ’0’ (R/W = 0) is placed on thebus and indicates to the addressed device thatword address An will follow and is to be written tothe on-chip address pointer. The data word to bewritten to the memory is strobed in next and the in-ternal address pointer is incremented to the nextmemory location within the RAM on the receptionof an acknowledge clock. The M41T11 slave re-ceiver will send an acknowledge clock to the mas-ter transmitter after it has received the slaveaddress and again after it has received the wordaddress and each data byte (see Figure 9).READ MODE
In this mode, the master reads the M41T11 slaveafter setting the slave address (see Figure 11).Following the write mode control bit (R/W = 0) andthe acknowledge bit, the word address An is writ-
ten to the on-chip address pointer. Next theSTART condition and slave address are repeated,followed by the READ mode control bit (R/W=1).At this point, the master transmitter becomes themaster receiver. The data byte which was ad-dressed will be transmitted and the master receiv-er will send an acknowledge bit to the slavetransmitter. The address pointer is only increment-ed on reception of an acknowledge bit. TheM41T11 slave transmitter will now place the databyte at address An + 1 on the bus. The master re-ceiver reads and acknowledges the new byte andthe address pointer is incremented to An + 2.
This cycle of reading consecutive addresses willcontinue until the master receiver sends a STOPcondition to the slave transmitter.
An alternate READ mode may also be implement-ed, whereby the master reads the M41T11 slavewithout first writing to the (volatile) address point-er. The first address that is read is the last onestored in the pointer, see Figure 12.
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M41T11
Figure 6. Serial Bus Data Transfer SequenceDATA LINESTABLEDATA VALIDCLOCKDATA STARTCONDITIONCHANGE OFDATA ALLOWEDSTOPCONDITIONAI00587Figure 7. Acknowledgment SequenceCLOCK PULSE FORACKNOWLEDGEMENT1289STARTSCLK FROMMASTERDATA OUTPUTBY TRANSMITTERDATA OUTPUTBY RECEIVERMSBLSBAI00601CLOCK OPERATION
The eight byte clock register (see Table 3) is usedto both set the clock and to read the date and timefrom the clock, in a binary coded decimal format.Seconds, Minutes, and Hours are contained withinthe first three registers. Bits D6 and D7 of clockregister 2 (Hours Register) contain the CENTURYENABLE Bit (CEB) and the CENTURY Bit (CB).Setting CEB to a ’1’ will cause CB to toggle, eitherfrom ’0’ to ’1’ or from ’1’ to ’0’ at the turn of the cen-tury (depending upon its initial state). If CEB is setto a ’0’, CB will not toggle. Bits D0 through D2 ofregister 3 contain the Day (day of week). Registers4, 5 and 6 contain the Date (day of month), Monthand Years. The final register is the Control Regis-ter (this is described in the Clock Calibration sec-tion). Bit D7 of register 0 contains the STOP Bit(ST). Setting this bit to a ’1’ will cause the oscillator
to stop. If the device is expected to spend a signif-icant amount of time on the shelf, the oscillatormay be stopped to reduce current drain. When re-set to a ’0’ the oscillator restarts within one second.The seven Clock Registers may be read one byteat a time, or in a sequential block. The ControlRegister (Address location 7) may be accessed in-dependently. Provision has been made to assurethat a clock update does not occur while any of theseven clock addresses are being read. If a clockaddress is being read, an update of the clock reg-isters will be delayed by 250ms to allow the readto be completed before the update occurs. Thiswill prevent a transition of data during the read.Note: This 250ms delay affects only the clock reg-ister update and does not alter the actual clocktime.
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M41T11
Figure 8. Bus Timing Requirements SequenceSDAtBUFtHD:STAtRSCLtHIGHPStLOWtSU:DATtHD:DATtSU:STASRPtSU:STOtFtHD:STAAI00589Note:P = STOP and S = STARTFigure 9. Slave Address LocationR/WSTARTSLAVE ADDRESSA1101000AI00602CLOCK CALIBRATION
The M41T11 is driven by a quartz controlled oscil-lator with a nominal frequency of 32,768Hz. Thedevices are tested not to exceed 35ppm (parts permillion) oscillator frequency error at 25°C, whichequates to about ±1.53 minutes per month. Withthe calibration bits properly set, the accuracy ofeach M41T11 improves to better than +1/–2 ppmat 25°C.
The oscillation rate of any crystal changes withtemperature (see Figure 14). Most clock chipscompensate for crystal frequency and tempera-ture shift error with cumbersome trim capacitors.The M41T11 design, however, employs periodic
counter correction. The calibration circuit adds orsubtracts counts from the oscillator divider circuitat the divide by 256 stage, as shown in Figure 13.The number of times pulses are blanked (subtract-ed, negative calibration) or split (added, positivecalibration) depends upon the value loaded intothe five bit Calibration byte found in the ControlRegister. Adding counts speeds the clock up, sub-tracting counts slows the clock down.
The Calibration byte occupies the five lower orderbits (D4-D0) in the Control register (Addr 7). Thisbyte can be set to represent any value between 0and 31 in binary form. Bit D5 is a Sign bit; '1' indi-cates positive calibration, '0' indicates negativecalibration. Calibration occurs within a 64minutecycle. The first 62 minutes in the cycle may, onceper minute, have one second either shortened by128 or lengthened by 256 oscillator cycles. If a bi-nary '1' is loaded into the register, only the first 2minutes in the 64 minute cycle will be modified; ifa binary 6 is loaded, the first 12 will be affected,and so on.
Therefore, each calibration step has the effect ofadding 512 or subtracting 256 oscillator cycles forevery 125,829,120 actual oscillator cycles, that is+4.068 or –2.034 ppm of adjustment per calibra-tion step in the calibration register. Assuming thatthe oscillator is in fact running at exactly 32,768Hz,each of the 31 increments in the Calibration bytewould represent +10.7 or –5.35 seconds permonth which corresponds to a total range of +5.5or –2.75 minutes per month.
MSB10/19
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M41T11
Figure 10. Write Mode SequenceSTARTBUS ACTIVITY:MASTERSDA LINESACKWORDADDRESS (n)ACKDATA nACKDATA n+1ACKDATA n+XBUS ACTIVITY:SLAVEADDRESSAI00591Figure 11. Read Mode SequenceSTARTSTARTR/WBUS ACTIVITY:MASTERSDA LINESACKWORDADDRESS (n)SACKACKR/WDATA nACKDATA n+1ACKAI00899BUS ACTIVITY:SLAVEADDRESSSLAVEADDRESSSTOPDATA n+XPNO ACKFigure 12. Alternate Read Mode SequenceSTARTBUS ACTIVITY:MASTERSDA LINESACKDATA nACKDATA n+1ACKACKDATA n+XBUS ACTIVITY:SLAVEADDRESSAI00895NO ACKSTOPPR/WACKSTOPPR/W11/19
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M41T11
Figure 13. Clock CalibrationNORMALPOSITIVECALIBRATIONNEGATIVECALIBRATIONAI00594BTwo methods are available for ascertaining howmuch calibration a given M41T11 may require.The first involves simply setting the clock, letting itrun for a month and comparing it to a known accu-rate reference (like WWV broadcasts). While thatmay seem crude, it allows the designer to give theend user the ability to calibrate his clock as his en-vironment may require, even after the final productis packaged in a non-user serviceable enclosure.All the designer has to do is provide a simple utilitythat accessed the Calibration byte.
The second approach is better suited to a manu-facturing environment, and involves the use ofsome test equipment. When the Frequency Test(FT) bit, the seventh-most significant bit in theControl Register, is set to a '1', and the oscillator isrunning at 32,768Hz, the FT/OUT pin of the devicewill toggle at 512Hz. Any deviation from 512Hz in-dicates the degree and direction of oscillator fre-quency shift at the test temperature.
For example, a reading of 512.01024Hz would in-dicate a +20ppm oscillator frequency error, requir-ing a –10(XX001010) to be loaded into theCalibration Byte for correction. Note that setting orchanging the Calibration Byte does not affect theFrequency test output frequency.
OUTPUT DRIVER PIN
When the FT bit is not set, the FT/OUT pin be-comes an output driver that reflects the contents ofD7 of the control register. In other words, when D6of location 7 is a zero and D7 of location 7 is a zeroand then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which re-quires an external pull-up resistor.
POWER-ON DEFAULTS
Upon initial application of power to the device, theFT bit will be set to a '0' and the OUT bit will be setto a '1'. All other Register bits will initially power-onin a random state.
12/19
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M41T11
Figure 14. Crystal Accuracy Across TemperatureFrequency (ppm)200–20–40–60–80–100–120–140–160–40–30–20–1001020304050607080∆F= -0.038ppm(T - T)2 ± 10%0FC2T0 = 25 °CTemperature °CAI0099913/19
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M41T11
Table 11. Ordering Information Scheme
Example:Device TypeM41T
Package
M = SO8 150mil WidthMH = SOH28Temperature Range6 = –40 to 85 °C
Shipping Method for SOblank = TubesTR = Tape & Reel
M41T11
M
6
TR
Note:The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
\"M4Txx-BR12SHx\" in plastic tube or \"M4Txx-BR12SHxTR\" in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package \"M4Txx-BR12SHx\" in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options or for further information on any aspect of this device, please contact theSTMicroelectronics Sales Office nearest to you.
Table 12. Revision History
DateMarch 199912/23/9905/22/00
First Issue
SOH28 package addedRS value change (Table 8)
Revision Details
14/19
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M41T11
Table 13. SO8 - 8 pin Plastic Small Outline, 150 mils body width, Package Mechanical Data
SymbAA1BCDEeHhLαNCP
1.27
mm
Typ
Min1.350.100.330.194.803.80–5.800.250.400°8
0.10Max1.750.250.510.255.004.00–6.200.500.908°
0.050Typ
inchesMin0.0530.0040.0130.0070.1890.150–0.2280.0100.0160°8
0.004Max0.0690.0100.0200.0100.1970.157–0.2440.0200.0358°
Figure 15. SO8 - 8 pin Plastic Small Outline, 150 mils body width, Package Outlineh x 45˚ACBeDCPNE1HA1αLSO-aDrawing is not to scale.15/19
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M41T11
Table 14. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT,Package Mechanical Data
SymbAA1A2BCDEeeBHLαNCP
1.27
0.052.340.360.1517.718.23–3.2011.510.410°28
0.10
mm
Typ
Min
Max3.050.362.690.510.3218.498.89–3.6112.701.278°
0.050
0.0020.0920.0140.0060.6970.324–0.1260.4530.0160°28
0.004
Typ
inches Min
Max0.1200.0140.1060.0200.0120.7280.350–0.1420.5000.0508°
Figure 16. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package OutlineA2BeACCPeBDNEHA1αL1SOH-ADrawing is not to scale.16/19
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M41T11
Table 15. M4T28-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
SymbAA1A2A3BDEeBL
0.4621.2114.223.202.036.736.48mm
Typ
Min
Max9.787.246.990.380.5621.8414.993.612.29
0.0180.8350.5600.1260.0800.2650.255
Typ
inchesMin
Max0.3850.2850.2750.0150.0220.8600.5900.1420.090
Figure 17. M4T28-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package OutlineA1AA3A2eADBeBLESHTK-ADrawing is not to scale.17/19
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M41T11
Table 16. M4T32-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
SymbAA1A2A3BDEeBL
0.4621.2117.273.202.038.007.24mm
Typ
Min
Max10.548.518.000.380.5621.8418.033.612.29
0.0180.8350.6800.1260.0800.3150.285
Typ
inchesMin
Max0.4150.3350.3150.0150.0220.8600.7100.1420.090
Figure 18. M4T32-BR12SH - TIMEKEEPER 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package OutlineA1AA3A2eADBeBLESHTK-BDrawing is not to scale.18/19
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M41T11
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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